1. Field of the Invention
The present invention relates to clock switching circuitry for switching clock signals different in phase from each other for thereby reducing jitter. More particularly, the present invention relates to clock switching circuitry applicable to, e.g., a receiver for receiving data input from the outside or a reproducing device for reading out data from a recording medium and reproducing the data.
2. Description of the Background Art
It is a common practice with, e.g., a receiver included in a transmission system or a video reproducing device to sample input data with a clock signal particular to the receiver or device and reproduce a signal from the sampled data. The input data involves phase errors, or jitter, with respect to a bilevel reference signal. To cope with the phase errors, the receiver or device mentioned above usually includes clock switching circuitry.
The clock switching circuitry switches a clock select signal in accordance with the phase error or jitter of the individual clock for thereby feeding a sampling circuit with a clock signal selected such that the sampling circuit can accurately sample data. A problem with the conventional clock switching circuitry is that when the switchover of the clock select signal is not coincident with the positive-going edge of the clock signal selected, the clock signal is apt to go high two consecutive times for a single data. The sampling circuit, when received the clock signal gone high two times for a single data, samples single data two consecutive times, as may be referred to as double sampling. As a result, in a device or a system including the clock switching circuitry, it is likely that the input data fails to match, e.g., a preselected format and is erroneously fed.
The data not matching the preselected format cannot be correctly processed at the time of reproduction. This brings about malfunction or causes a resend command to be transmitted to a source station due to error detection. Processing necessary for avoiding such errors ascribable to the clock switching circuitry critically lowers the processing ability of the device or the system.
Moreover, the sampled data is synchronous to the sampling clock signal generated by the clock switching circuitry and is therefore used in the device or the system as well. Consequently, the clock signal erroneously including two consecutive pulses for single data prevents a synchronizing circuit included in the device or the system from operating at an expected timing and causes it to malfunction.
In light of the above, the conventional clock switching circuitry includes a first and a second clock selector with a clock selecting function, a register with a synchronous enabling function and a switching clock enable generator that are configured to switch the clock signal while accurately following phase errors. To the clock switching circuitry, a clock generator is connected for feeding beforehand a plurality of clock signals different in phase from each other. Also, to the select terminal of the first clock selector of the clock switching circuitry and the input terminal of the register, clock select data is delivered from a clock select signal generator.
The clock generator includes a PLL (Phase Locked Loop) circuit for generating a high-speed clock signal higher in clock rate than the plurality of clock signals described above. The high-speed clock signal is generated in such a manner that each of the plurality of clock signals is provided with a phase error that is equal to an integral multiple of one period of the high-speed clock signal.
The first clock selector delivers one of the clock signals designated by the clock select signal to the switching clock enable generator. The register feeds the second clock selector with a phase-corrected select signal. The second clock selector delivers a sampling clock to a sampling circuit or flip-flop circuit and the switching clock enable generator in response to the phase-corrected select signal. The switching clock enable generator detects the switching timing of the clock signals fed from the first and second clock selectors. The switching clock enable generator then feeds the register with an enable signal such that the register stores, after the above timing, data fed thereto as a clock select signal. During the enable period of the enable signal, the register samples the data at the first positive-going edge of the high-speed clock signal and delivers corrected, selected data to the second clock selector.
With the above configuration, the clock switching circuitry feeds the waveform of one clock signal corresponding to the data, which is input to the second clock selector, to the flip-flop circuit as a sampling clock signal. By sampling input data with the sampling clock signal, the flip-flop circuit surely samples the data while correcting phase errors. At the same time, the device or the system using the sampling clock as its system clock operates in a stable manner. The conventional clock switching circuitry will be described more specifically.
The conventional clock switching circuitry generates the enable signal in response to the high-speed clock signal input from the outside and the switchover of the clock, as stated above. This allows the device or the system including such a clock switching circuitry to perform flexible operation, including data sampling, with phase errors being adjusted in synchronism with the timing of the high-speed clock signal. The clock switching circuitry, however, needs a number of parts for reducing jitter. Further, the clock generator must be configured to output the high-speed clock signal higher in speed than the clock signals having phase errors. Consequently, the clock switching circuitry and therefore the entire device or system using it is bulky.